数据结构设计

enum spi_mode_type {
    SINGLE_HALF_DUPLEX_RX,
    SINGLE_HALF_DUPLEX_TX,
    SINGLE_FULL_DUPLEX_RX_TX,
    DUAL_HALF_DUPLEX_RX,
    DUAL_HALF_DUPLEX_TX,
    QUAD_HALF_DUPLEX_RX,
    QUAD_HALF_DUPLEX_TX,
    MODE_TYPE_NULL,
};

struct aic_spi {
    struct device *dev;                 // 设备指针
    struct spi_controller *ctlr;        // SPI CORE 的控制器指针
    void __iomem *base_addr;            // 映射后的 SPI 控制器地址
    struct clk *mclk;                   // SPI 控制器的时钟
    struct reset_control *rst;          // SPI 控制器的复位
    struct dma_chan *dma_rx;            // SPI 控制器的接收 DMA Channel
    struct dma_chan *dma_tx;            // SPI 控制器的发送 DMA Channel
    dma_addr_t dma_addr_rx;             // SPI 控制器 RX FIFO 地址
    dma_addr_t dma_addr_tx;             // SPI 控制器 TX FIFO 地址
    enum spi_mode_type mode_type;
    unsigned int irq;                   // 中断号
    char dev_name[48];
    spinlock_t lock;
};

struct qspi_master_config {
    uint32_t idx;
    uint32_t clk_in_hz;
    uint32_t clk_id;
    bool bit_mode;
    bool wire3_en;
    bool lsb_en;
    bool cs_auto;
    uint8_t cs_polarity;
    uint8_t cpol;
    uint8_t cpha;
};

struct qspi_master_dma_config {
    uint32_t port_id;
    uint32_t tx_bus_width;
    uint32_t tx_max_burst;
    uint32_t rx_bus_width;
    uint32_t rx_max_burst;
};

struct qspi_transfer {
    uint8_t *tx_data;
    uint8_t *rx_data;
    uint32_t data_len;
};

struct qspi_master_state {
    uint32_t idx;
    qspi_master_async_cb cb;
    void *cb_priv;
    uint32_t status;
    uint32_t clk_id;
    uint32_t bus_hz;
    uint32_t bus_width;
    struct qspi_master_dma_config dma_cfg;
    void *dma_tx;
    void *dma_rx;
    uint8_t *async_tx; /* Used in Async Non-DMA mode */
    uint8_t *async_rx; /* Used in Async Non-DMA mode */
    uint32_t async_tx_remain; /* Used in Async Non-DMA mode */
    uint32_t async_rx_remain; /* Used in Async Non-DMA mode */
    uint32_t work_mode;
    uint32_t done_mask;
};